DRAMs (dynamic random access memories) which have come to be widely used in recent years are generally of the synchronous type, operating synchronously with an external clock signal supplied from a memory controller. The external clock signal is supplied to a clock signal generation circuit provided inside the DRAM, and as a result an internal clock signal which is a base clock within the DRAM is generated (see Patent Document 1).
Generally speaking, the internal clock signal is always clocked during normal operation so that it is possible to respond whenever a command is issued and whatever type of command is issued from the memory controller.